1. Field of the Invention
The present invention relates to an element substrate for an inkjet printhead, a printhead having the element substrate, and a head cartridge. Particularly, the present invention relates to an element substrate on which heaters for generating heat energy necessary to discharge ink, and driving circuits for driving them are formed, a printhead having the element substrate, and a head cartridge.
2. Description of the Related Art
As disclosed in the U.S. Pat. No. 6,290,334, the heaters of a conventional inkjet printhead and their driving control circuits are formed on a single element substrate by a semiconductor process. An element substrate which integrates heater and driving control circuits can take a variety of layouts. FIG. 8 shows an example of the layout.
An ink supply port 901 is formed near the center on an element substrate 900 shown in FIG. 8 to supply ink from the lower surface of the element substrate. Heater sections 902, switching element sections 903, heater selection circuit sections 904, voltage conversion circuit sections 905, and shift register sections 906 are arranged to face each other via the ink supply port 901.
Pads 907 of power supply terminals for receiving driving voltages for heaters and respective circuits, and signal terminals for outputting various signals to them are arranged on the shorter sides of the element substrate 900, and connected to heaters and respective circuits via aluminum wiring lines.
A printhead which employs, for example, an NMOS transistor as a heater switching element needs to improve the drivability of the NMOS transistor. For this purpose, the voltage conversion circuit section 905 is arranged to apply, to the gate of the NMOS transistor, a voltage VHT obtained by boosting a driving voltage VDD for a logic circuit on the element substrate, as disclosed in the U.S. Pat. No. 6,302,504. There has conventionally been known a circuit arrangement which employs a voltage of about 3.3 V or 5 V as the driving voltage VDD.
FIG. 9 is a block diagram showing an example of conventional heaters and their driving control circuits. In FIG. 9, a heater 101 serves as a printing element. An NMOS transistor 102 serves as a switching element for driving each heater. A heater selection circuit 1003 receives logical signals, and calculates the logical product. A shift register (S/R) +latch (Latch) 104 stores, in synchronism with a clock signal CLK, a block control signal input as a serial signal from the printing apparatus main body, and latches it in accordance with a latch signal LT. A 1-bit shift register+latch 105 stores, in synchronism with the clock signal, print data DATA input as a serial signal from the printing apparatus main body, and latches it in accordance with the latch signal. A block selection circuit (X to N Decoder) 106 decodes an X-bit block control signal input from the printing apparatus main body to select one of N block selection signal lines in accordance with a block selection signal BLE. At the end of the element substrate, N voltage conversion circuits A 107 are arranged, corresponding to the number (N) of block selection signal lines. One of M voltage conversion circuits 1008 is arranged in a corresponding one of adjacent groups 110 each including N heaters 101, N NMOS transistors 102, and N heater selection circuits 1003.
M 1-bit shift registers+latches 105 are arranged in correspondence with groups 1 to M. The output of each 1-bit shift register is connected to the input of an adjacent 1-bit shift register. The output of the 1-bit latch 105 is connected to the input of the voltage conversion circuit 1008 of a corresponding group. The output of the voltage conversion circuit 1008 is connected to the input of the heater selection circuit 1003 of a corresponding group. The output of each voltage conversion circuits A 107 arranged at the end of the element substrate is connected to the inputs of the heater selection circuits 1003 in a corresponding one of blocks 1 to N in groups 1 to M. In FIG. 9, the 1-bit shift registers+latches 105 each functions as 1-bit shift registers, and form an M-bit shift register as a whole.
The operations of the heaters and their driving control circuits shown in FIG. 9 will be explained with reference to the timing chart of FIG. 10.
M-bit data corresponding to print data DATA are serially transferred to the shift register+latch 104 and 1-bit shift registers+latches 105 in synchronism with the clock signal CLK. The latch signal LT changes to High, and the print data is input to the 1-bit shift registers+latches 105. The signal level of a predetermined one of M output lines extending from the 1-bit shift registers+latches 105 changes to High in accordance with the print data.
Similarly, X-bit block control signals are also serially input to the shift register+latch 104 in synchronism with the clock signal. Then, the latch signal changes to High, and the X-bit block control signals are input to the block selection circuit 106. The timing of the block selection signal BLE output from the block selection circuit 106 to an output line 112 corresponds to the timing of BLE in FIG. 10. The X-bit block control signals select one of N voltage conversion circuits A 107 to which the block selection signal is input. A predetermined heater is selected by a heater selection circuit 1003 selected by a High block control signal from M heater selection circuits 1003 commonly connected to one output signal extending from the voltage conversion circuit A 107. A current I flows through the selected heater in accordance with a heating enable signal HE, thereby driving the heater.
The above-described operation is sequentially repeated N times. As a result, M×N heaters can be time-divisionally driven every M heaters at N timings, thereby driving all the heaters.
Similar to the voltage conversion circuit section 905 shown in FIG. 8, the voltage conversion circuit A 107 and voltage conversion circuit 1008 shown in FIG. 9 are arranged to apply, to the gate of the NMOS transistor, the voltage VHT obtained by boosting the driving voltage VDD for a logic circuit on the element substrate.
FIG. 11 is a circuit diagram showing the voltage conversion circuit 1008.
In FIG. 11, reference numerals 1201 to 1210 denote building elements of the voltage conversion circuit 1008. The terminal IN 1201 receives a signal output from a logic circuit such as the block selection circuit. The inverter 1202 inverts the logic of a signal input from the terminal IN 1201 to output the inverted signal. The MOS transistors 1203 to 1208 form a voltage converter which converts the voltage of a signal. The inverter 1209 buffers a signal output from the voltage conversion circuit 1008. The terminal OUT 1210 outputs a voltage-converted signal.
A signal input to the terminal IN 1201 is input to the gates of the PMOS transistor 1207 and NMOS transistor 1206, and the inverter 1202. A signal logic-inverted by the inverter 1202 is input to the gates of the PMOS transistor 1204 and NMOS transistor 1203. A signal input to the terminal IN 1201 and a signal output from the inverter 1202 have the voltage VDD.
When a signal of the voltage VDD is input to the terminal IN 1201, a voltage of 0 V is applied to the gates of the MOS transistors 1203 and 1204 because the inverted signal of the signal input to the terminal IN 1201 is input to them. The voltage VDD is applied to the gates of the MOS transistors 1206 and 1207 because a signal input to the terminal IN 1201 is directly input to them. At this time, the gate of the NMOS transistor 1206 is turned on to connect its drain to ground GND at low impedance. The drain of the NMOS transistor 1206 is connected to the gate of the PMOS transistor 1205. Thus, the gate of the PMOS transistor 1205 is connected to GND at low impedance to turn on the PMOS transistor 1205. The gate of the PMOS transistor 1204 series-connected to the PMOS transistor receives an output signal from the inverter 1202, so the gate voltage of the PMOS transistor 1204 becomes 0V. At this time, the PMOS transistor 1204 remains ON regardless of whether VDD or 0 V is applied to its gate. This is because the PMOS transistor 1205 is ON, and the source voltage of the PMOS transistor 1204 is VHT higher than VDD. Further, the gate voltage of the NMOS transistor 1203 series-connected to the PMOS transistor is 0 V, so the NMOS transistor 1203 is turned off. Since the PMOS transistors 1205 and 1204 are ON and the NMOS transistor 1203 is OFF, the voltage of a node connected to the drains of the PMOS transistor 1204 and NMOS transistor 1203 and the gate of the PMOS transistor 1208 becomes the power supply voltage VHT of the voltage conversion circuit. Since the gate voltage of the PMOS transistor 1208 changes to VHT, the PMOS transistor 1208 is turned off. Since the NMOS transistor 1206 is ON, the voltage of a node connected to the drains of the PMOS transistor 1207 and NMOS transistor 1206 and the gate of the PMOS transistor becomes 0 V. An output signal from the inverter connected to this node serves as an output signal from the voltage conversion circuit A. Since the voltage of the node connected to the inverter 1209 is 0 V, a signal of the voltage VHT is output from the terminal OUT 1210.
When the level of a signal input to the terminal IN 1201 is Low, the logic of each element of the voltage conversion circuit A becomes opposite to the above-mentioned one. Thus, no signal is output from the terminal OUT 1210.
FIG. 12 is a circuit diagram showing the heater selection circuit 1003 in FIG. 9.
The heater selection circuit 1003 includes two PMOS transistors 1301 and 1302 series-connected to a power supply for outputting the voltage VHT. The heater selection circuit 1003 also includes two NMOS transistors 1303 and 1304, whose drains are connected to that of the PMOS transistor 1302, parallel-connected to the PMOS transistor 1302. The heater selection circuit 1003 takes a two-input NOR circuit in which the gates of the PMOS transistor 1301 and NMOS transistor 1303 are connected to the terminal IN1, and those of the PMOS transistor 1302 and NMOS transistor 1304 are connected to the terminal IN2. When both the terminals IN1 and IN2 receive High signals, a signal output from the terminal OUT changes to Low. In other cases, a signal output from the terminal OUT also changes to HIGH, outputting the voltage VHT. The terminals IN1 and IN2 receive signals with an amplitude of 0 V to VHT boosted up to the voltage VHT by the voltage conversion circuit, selecting a heater.
FIG. 13 is a timing chart showing the input timings of input signals to the voltage conversion circuit and the application timing of the gate voltage to the NMOS transistor serving as a switching element when driving a heater on a conventional element substrate.
A print data signal HEAT output from a print data supply circuit to determine a timing to supply a driving current to a heater is input with an amplitude of 0 V to VDD to the terminal IN of the voltage conversion circuit. In response to the timing of HEAT, a current IHT consumed by a power supply for driving an NMOS transistor serving as a switching element transiently flows at the leading and trailing edges of the HEAT pulse.
An NMOS transistor serving as a switching element corresponding to a heater selected as a heater to be driven is connected to the voltage conversion circuit. A signal OUT_on (VG_on) with an amplitude of 0 V to VHT is applied to the gate of the NMOS transistor. The signal OUT_on is obtained by converting the voltage of HEAT. The NMOS transistor serving as a switching element to which OUT_on is applied to its gate is turned on while a gate voltage equal to or higher than a threshold Vth is applied. A 50-mA current IH_on flows through a corresponding heater.
To the contrary, no voltage is applied to an NMOS transistor serving as a switching element corresponding to a heater not selected as a heater to be driven, as represented by OUT_off (VG_off). As represented by IH_off, no current flows through a corresponding heater.
Recently, the above-described inkjet printing apparatus is increasing the nozzle arrangement density in order to implement high-speed, high-quality printing. The inkjet printing apparatus which prints by scanning the printhead can increase the width of printing by one scanning by increasing the number of heaters in order to achieve high-speed printing. However, this increases the area of the element substrate of the printhead. Also, the inkjet printing apparatus can downsize a droplet discharged from the printhead in order to achieve high-quality printing. In this case, to prevent a decrease in printing speed while downsizing the droplet, the number of nozzles must be increased to arrange them at high density. As a result, heater driving circuits and the like must be arranged on the element substrate in correspondence with a narrow heater pitch, increasing the area of the element substrate in a direction perpendicular to the nozzle arrayed direction. The increase in the area of the element substrate raises the cost. The length of the element substrate in the nozzle arrayed direction is determined by the printing width. To reduce the area of the element substrate, the length in a direction perpendicular to the nozzle arrayed direction must be shortened.
On an element substrate having the conventional arrangement shown in FIG. 8, shift registers are arranged along the nozzle arrayed direction. On the element substrate, data flows through the shift register, voltage conversion circuit, and heater selection circuit in the order named. The voltage conversion circuit and heater selection circuit must be interposed between the shift register and the heater. Thus, the voltage conversion circuit and heater selection circuit are also arranged along the nozzle arrayed direction in accordance with the arrangement of the heater and shift register. The above-described voltage conversion circuit has many building elements in order to prevent a breakthrough current from flowing. These building elements occupy a large area of the element substrate in the nozzle arrayed direction. A circuit, such as the voltage conversion circuit, which needs to operate at high voltage must have a high-voltage tolerant structure in order to ensure tolerance against high voltage. However, integration for the high-voltage tolerant structure is limited, and it is difficult to integrate elements at high density. As another conceivable countermeasure except for the high-density integration, the number of building elements such as transistors may also be reduced. However, each transistor which forms a conventional voltage conversion circuit is necessary to cut off a current flowing through the voltage conversion circuit upon switching.